In general, a built-in self test (BIST) module for testing a memory is formed as part of a large-scale integrated circuit (LSI) together with a user circuit for operating the memory. The BIST module is provided with a counter able to count up/down for successively designating addresses of a memory. When connecting a BIST module to a memory and running a memory test, data is written to and read from all addresses of the memory. At this time, all addresses of the memory are designated while the up/down counter increments its count from the minimum value to the maximum value of the addresses. Next, all addresses of the memory are designated while the up/down counter decrements its count from the maximum value to the minimum value of the address.
In this regard, when testing the operation of the LSI itself including the BIST module, the test is performed without connecting a memory. The LSI is tested by operating the counter, monitoring the LSI terminals, and comparing the value output from the counter and the anticipated value. In the past, to serially operating the test sequence, after the up operation of the up/down counter, a down operation of the up/down counter was performed. However, since the up operation of the counter is followed by a down operation, enormous time was taken for testing the counter.
Note that to raise the operating frequency of the counter, it is known to provide an odd counter and an even counter to perform parallel operations. Further, a parallel type error counter circuit counting the error data bits transmitted in parallel by a simple circuit configuration is known (see Japanese Laid Open Patent Publication No. 8-184440 and Japanese Laid Open Patent Publication No. 1-238317)